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other82 active rulesVerified 2026-09-30

Xilinx .gitignore Template

Standard Xilinx gitignore template from upstream github/gitignore collection. Generated and merged deterministically with upstream GitHub repository patterns to keep your repository clean of package directories, temporary build artifacts, and local environment files.

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.gitignore
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### Xilinx ###
# gitignore template for Xilinx Vivado Design Suite
# website: https://www.xilinx.com/support/download.html
# [home]
*.jou
*.log
*.debug
*.str
*.zip
*.tmp
*.rst
*.os
*.js
*.pb
*.dcp
*.hwdef
*.vds
*.veo
*.wdf
*.vdi
*.dmp
*.rpx
*.rpt
*_stub.v
*_stub.vhdl
*_funcsim.v
*_funcsim.vhdl
.project
# [dir]
*.cache
.metadata
*.data
*.ipdefs
.Xil
*.sdk
*.hw
*.ip_user_files
### IP synth
*_synth_*
.jobs
### project synth
*/*.runs/synth*/*.xml
*/*.runs/synth*/*.txt
*/*.runs/synth*/*.sh
*/*.runs/synth*/*.tcl
*/*.runs/synth*/*.bat
*/*.runs/synth*/*.xdc
!*/*.runs/synth*/*utilization*.rpt
*.runs/synth*/*.xml
*.runs/synth*/*.txt
*.runs/synth*/*.sh
*.runs/synth*/*.tcl
*.runs/synth*/*.bat
*.runs/synth*/*.xdc
!*.runs/synth*/*utilization*.rpt
### project impl
*/*.runs/impl*/*.xml
*/*.runs/impl*/*.html
*/*.runs/impl*/*.txt
*/*.runs/impl*/*.sh
*/*.runs/impl*/*.tcl
*/*.runs/impl*/*.bat
!*/*.runs/impl*/*utilization*.rpt
*.runs/impl*/*.xml
*.runs/impl*/*.html
*.runs/impl*/*.txt
*.runs/impl*/*.sh
*.runs/impl*/*.tcl
*.runs/impl*/*.bat
!*.runs/impl*/*utilization*.rpt
### block design
*/*/bd/*/hdl
*/*/*/bd/*/hdl
*/*/bd/*/*.xdc
*/*/*/bd/*/*.xdc
*/*/bd/*/ip/*/*.xdc
*/*/*/bd/*/ip/*/*.xdc
*/*/bd/*/ip/*/*/
*/*/*/bd/*/ip/*/*/
*/*/bd/*/ip/*/*.vhd
*/*/*/bd/*/ip/*/*.vhd
*/*/bd/*/ip/*/*.xml
*/*/*/bd/*/ip/*/*.xml
*.c
*.h
*.vho
*.html
*/*/bd/*/ip/*/*.tcl
*/*/*/bd/*/ip/*/*.tcl
hw_handoff
ipshared
107 lines•UTF-8
Deterministic

Raw Xilinx .gitignore

Crawlable upstream source template
xilinx.gitignore•106 lines•UTF-8
# gitignore template for Xilinx Vivado Design Suite
# website: https://www.xilinx.com/support/download.html
# [home]
*.jou
*.log
*.debug
*.str
*.zip
*.tmp
*.rst
*.os
*.js
*.pb
*.dcp
*.hwdef
*.vds
*.veo
*.wdf
*.vdi
*.dmp
*.rpx
*.rpt
*_stub.v
*_stub.vhdl
*_funcsim.v
*_funcsim.vhdl
.project
# [dir]
*.cache
.metadata
*.data
*.ipdefs
.Xil
*.sdk
*.hw
*.ip_user_files
### IP synth
*_synth_*
.jobs
### project synth
*/*.runs/synth*/*.xml
*/*.runs/synth*/*.txt
*/*.runs/synth*/*.sh
*/*.runs/synth*/*.tcl
*/*.runs/synth*/*.bat
*/*.runs/synth*/*.xdc
!*/*.runs/synth*/*utilization*.rpt
*.runs/synth*/*.xml
*.runs/synth*/*.txt
*.runs/synth*/*.sh
*.runs/synth*/*.tcl
*.runs/synth*/*.bat
*.runs/synth*/*.xdc
!*.runs/synth*/*utilization*.rpt
### project impl
*/*.runs/impl*/*.xml
*/*.runs/impl*/*.html
*/*.runs/impl*/*.txt
*/*.runs/impl*/*.sh
*/*.runs/impl*/*.tcl
*/*.runs/impl*/*.bat
!*/*.runs/impl*/*utilization*.rpt
*.runs/impl*/*.xml
*.runs/impl*/*.html
*.runs/impl*/*.txt
*.runs/impl*/*.sh
*.runs/impl*/*.tcl
*.runs/impl*/*.bat
!*.runs/impl*/*utilization*.rpt
### block design
*/*/bd/*/hdl
*/*/*/bd/*/hdl
*/*/bd/*/*.xdc
*/*/*/bd/*/*.xdc
*/*/bd/*/ip/*/*.xdc
*/*/*/bd/*/ip/*/*.xdc
*/*/bd/*/ip/*/*/
*/*/*/bd/*/ip/*/*/
*/*/bd/*/ip/*/*.vhd
*/*/*/bd/*/ip/*/*.vhd
*/*/bd/*/ip/*/*.xml
*/*/*/bd/*/ip/*/*.xml
*.c
*.h
*.vho
*.html
*/*/bd/*/ip/*/*.tcl
*/*/*/bd/*/ip/*/*.tcl
hw_handoff
ipshared

Key Pattern Breakdown

Build Outputs & Compiled Artifacts

Generated binary files, compilation targets, and distribution bundles that can be reliably reproduced from source.

*.os

Execution Caches & Runtime Logs

Diagnostic logs, runtime metadata, test coverage reports, and incremental compiler caches that cause noisy repository diffs.

*.log*.tmp*.cache

Source & Verification

License: CC0-1.0

Place this file in the root directory of your project as .gitignore. Changes take effect on newly added or untracked files.