Synopsys VCS Modèle .gitignore

1### Synopsys VCS ###
2# Waveform formats
3*.vcd
4*.vpd
5*.evcd
6*.fsdb
7 
8# Default name of the simulation executable.  A different name can be
9# specified with this switch (the associated daidir database name is
10# also taken from here):  -o <path>/<filename>
11simv
12 
13# Generated for Verilog and VHDL top configs
14simv.daidir/
15simv.db.dir/
16 
17# Infrastructure necessary to co-simulate SystemC models with
18# Verilog/VHDL models.  An alternate directory may be specified with this
19# switch:  -Mdir=<directory_path>
20csrc/
21 
22# Log file - the following switch allows to specify the file that will be
23# used to write all messages from simulation:  -l <filename>
24*.log
25 
26# Coverage results (generated with urg) and database location.  The
27# following switch can also be used:  urg -dir <coverage_directory>.vdb
28simv.vdb/
29urgReport/
30 
31# DVE and UCLI related files.
32DVEfiles/
33ucli.key
34 
35# When the design is elaborated for DirectC, the following file is created
36# with declarations for C/C++ functions.
37vc_hdrs.h
38