other14 regras ativasVerificado em 2026-09-30

Synopsys VCS Modelo de .gitignore

Standard Synopsys VCS gitignore template from upstream github/gitignore collection. Gerado e mesclado de forma determinística com os padrões oficiais do GitHub para manter seu repositório livre de pastas de pacotes, artefatos de compilação e arquivos de ambiente local.

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Synopsys VCS

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Standard Synopsys VCS gitignore template from upstream github/gitignore collection

#synopsysvcs

.gitignore

14 regras•1 modelo

1### Synopsys VCS ###
2# Waveform formats
3*.vcd
4*.vpd
5*.evcd
6*.fsdb
7 
8# Default name of the simulation executable.  A different name can be
9# specified with this switch (the associated daidir database name is
10# also taken from here):  -o <path>/<filename>
11simv
12 
13# Generated for Verilog and VHDL top configs
14simv.daidir/
15simv.db.dir/
16 
17# Infrastructure necessary to co-simulate SystemC models with
18# Verilog/VHDL models.  An alternate directory may be specified with this
19# switch:  -Mdir=<directory_path>
20csrc/
21 
22# Log file - the following switch allows to specify the file that will be
23# used to write all messages from simulation:  -l <filename>
24*.log
25 
26# Coverage results (generated with urg) and database location.  The
27# following switch can also be used:  urg -dir <coverage_directory>.vdb
28simv.vdb/
29urgReport/
30 
31# DVE and UCLI related files.
32DVEfiles/
33ucli.key
34 
35# When the design is elaborated for DirectC, the following file is created
36# with declarations for C/C++ functions.
37vc_hdrs.h
38

38 linhas•UTF-8•LF

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Código bruto de Synopsys VCS .gitignore

Modelo oficial original rastreável

synopsysvcs.gitignore•37 lines•UTF-8

1# Waveform formats
2*.vcd
3*.vpd
4*.evcd
5*.fsdb
6 
7# Default name of the simulation executable.  A different name can be
8# specified with this switch (the associated daidir database name is
9# also taken from here):  -o <path>/<filename>
10simv
11 
12# Generated for Verilog and VHDL top configs
13simv.daidir/
14simv.db.dir/
15 
16# Infrastructure necessary to co-simulate SystemC models with
17# Verilog/VHDL models.  An alternate directory may be specified with this
18# switch:  -Mdir=<directory_path>
19csrc/
20 
21# Log file - the following switch allows to specify the file that will be
22# used to write all messages from simulation:  -l <filename>
23*.log
24 
25# Coverage results (generated with urg) and database location.  The
26# following switch can also be used:  urg -dir <coverage_directory>.vdb
27simv.vdb/
28urgReport/
29 
30# DVE and UCLI related files.
31DVEfiles/
32ucli.key
33 
34# When the design is elaborated for DirectC, the following file is created
35# with declarations for C/C++ functions.
36vc_hdrs.h
37

Detalhamento de padrões essenciais

Cache e arquivos temporários

Ignora caches de compiladores, dados de cobertura de testes e arquivos de rascunho temporários.

*.log

Origem e verificação

Fonte:: GitHub gitignore (main)

Licença:: CC0-1.0

Coloque este arquivo na raiz do seu projeto com o nome .gitignore. As alterações passam a valer para arquivos novos ou não rastreados.

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Synopsys VCS Modelo de .gitignore

Gerador interativo de stack

Código bruto de Synopsys VCS .gitignore

Detalhamento de padrões essenciais

Cache e arquivos temporários

Origem e verificação

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