other14 active rulesVerified 2026-09-30
Synopsys VCS .gitignore Template
Standard Synopsys VCS gitignore template from upstream github/gitignore collection. Generated and merged deterministically with upstream GitHub repository patterns to keep your repository clean of package directories, temporary build artifacts, and local environment files.
Interactive Stack Generator
Preconfigured with Synopsys VCS/
Search for templates
Quick add:
Selected1
Synopsys VCS
Selected Templates (1)
Synopsys VCS
other
Standard Synopsys VCS gitignore template from upstream github/gitignore collection
#synopsysvcs
.gitignore
14 rules•1 template
### Synopsys VCS #### Waveform formats*.vcd*.vpd*.evcd*.fsdb # Default name of the simulation executable. A different name can be# specified with this switch (the associated daidir database name is# also taken from here): -o <path>/<filename>simv # Generated for Verilog and VHDL top configssimv.daidir/simv.db.dir/ # Infrastructure necessary to co-simulate SystemC models with# Verilog/VHDL models. An alternate directory may be specified with this# switch: -Mdir=<directory_path>csrc/ # Log file - the following switch allows to specify the file that will be# used to write all messages from simulation: -l <filename>*.log # Coverage results (generated with urg) and database location. The# following switch can also be used: urg -dir <coverage_directory>.vdbsimv.vdb/urgReport/ # DVE and UCLI related files.DVEfiles/ucli.key # When the design is elaborated for DirectC, the following file is created# with declarations for C/C++ functions.vc_hdrs.h 38 lines•UTF-8•LF
Deterministic
Raw Synopsys VCS .gitignore
Crawlable upstream source templatesynopsysvcs.gitignore•37 lines•UTF-8
# Waveform formats*.vcd*.vpd*.evcd*.fsdb # Default name of the simulation executable. A different name can be# specified with this switch (the associated daidir database name is# also taken from here): -o <path>/<filename>simv # Generated for Verilog and VHDL top configssimv.daidir/simv.db.dir/ # Infrastructure necessary to co-simulate SystemC models with# Verilog/VHDL models. An alternate directory may be specified with this# switch: -Mdir=<directory_path>csrc/ # Log file - the following switch allows to specify the file that will be# used to write all messages from simulation: -l <filename>*.log # Coverage results (generated with urg) and database location. The# following switch can also be used: urg -dir <coverage_directory>.vdbsimv.vdb/urgReport/ # DVE and UCLI related files.DVEfiles/ucli.key # When the design is elaborated for DirectC, the following file is created# with declarations for C/C++ functions.vc_hdrs.h Key Pattern Breakdown
Execution Caches & Runtime Logs
Diagnostic logs, runtime metadata, test coverage reports, and incremental compiler caches that cause noisy repository diffs.
*.log
Source & Verification
Source: GitHub gitignore (main)
License: CC0-1.0
Place this file in the root directory of your project as .gitignore. Changes take effect on newly added or untracked files.